1. Field of the Invention
The present invention relates to a class-F amplifier, and particularly, to a class-F amplifier of a high-frequency semiconductor device of class-F operation allowing the impedance, as it is seen from an amplifying element with a load inclusive, to be matched for a fundamental wave, shorted for even harmonics, and open for odd harmonics.
2. Description of the Related Art
Recent years have observed high-frequency operable transistors in practical use, such as HEMT (High Electron Mobility Transistor), HBT (Hetero-junction Bipolar Transistor), etc. Those devices implement operation frequencies within a band of 50 to 60 GHz.
Some of them make positive use of harmonics to allow for an enhanced gain, where desirable for enhanced power efficiency is controlled power consumption by harmonics.
For such a purpose so-called class-F amplifiers are used. For class-F amplifiers, the principle is to have a combination of instantaneous voltage waveform and instantaneous current waveform kept anytime from overlapping each other.
It therefore is necessary for a transistor to have an impedance seen from an output terminal thereof with the load side inclusive to be shorted for even harmonics, and open for odd harmonics. The transistor is thereby allowed for the current through the output terminal to have frequency components consisting simply of a fundamental and even harmonics, and for the voltage thereacross to have frequency components consisting simply of odd harmonics, with a nullified power loss due to harmonics. If the phase of a current in the fundamental is quite opposite to the voltage, dc power may be converted into microwave power with a 100% efficiency.
There has been disclosed in patent document 1 below, as well as patent document 2 below, a class-F amplifier in which the impedance seen from an amplifying element with a load inclusive is not simply matched for a fundamental wave, but also shorted for even harmonics and rendered open for odd harmonics, for the high frequency power amplifier to be enhanced in efficiency.
However, assuming the amplifying element to be an FET (Field Effect Transistor) of an internally matched FET model that has a dc bias Vdd supplied to the drain from an RF output terminal of an enclosure, for example, if it has built in a harmonic processor composed of a distributed constant circuit, as disclosed in patent document 1, then the distributed constant circuit might have an increased area, with a resultant increase in area of the enclosure.
On the other hand, as disclosed in patent document 2, one may employ a downsized harmonic processor composed of a lumped constant circuit to be open for a dc, and set in such a system that has a direct dc bias supplied to the drain of an FET via a choke coil separated from the harmonic processor, and is inapplicable to a high power internally matched FET having a dc bias supplied from an RF output terminal.
Both cases have an impedance seen from the drain of an FET, with a load inclusive, set open for odd harmonics, and would work for a class-F operation at frequencies where the output capacity of FET is negligible, but would not at high frequencies where the output capacity of FET is unnegligible.
Patent document 1:                Japanese Patent Application Laying-Open Publication No. 2001-111362        
Patent document 2:                Japanese Patent Application Laying-Open Publication No. 2005-117200        